1. Field of the Invention
The present invention relates to a thin film magnetic memory device. More particularly, the present invention relates to a random access memory (RAM) including memory cells having a magnetic tunnel junction (MTJ).
2. Description of the Background Art
An MRAM (Magnetic Random Access Memory) device has attracted attention as a memory device capable of non-volatile data storage with low power consumption. The MRAM device is a memory device that stores data in a non-volatile manner using a plurality of thin film magnetic elements formed in a semiconductor integrated circuit and is capable of random access to each thin film magnetic element.
In particular, recent announcement shows that significant progress in performance of the MRAM device is achieved by using thin film magnetic elements having a magnetic tunnel junction (MTJ) as memory cells. The MRAM device including memory cells having a magnetic tunnel junction is disclosed in technical documents such as xe2x80x9cA 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cellxe2x80x9d, ISSCC Digest of Technical Papers, TA7.2, February 2000, and xe2x80x9cNonvolatile RAM based on Magnetic Tunnel Junction Elementsxe2x80x9d, ISSCC Digest of Technical Papers, TA7.3, February 2000.
FIG. 41 is a schematic diagram showing the structure of a memory cell having a magnetic tunnel junction (hereinafter, also simply referred to as MTJ memory cell).
Referring to FIG. 41, the MTJ memory cell includes a magnetic tunnel junction MTJ having its resistance value varied according to the level of storage data, and an access transistor ATR. The access transistor ATR is formed by a field effect transistor, and is coupled between the magnetic tunnel junction MTJ and ground potential Vss.
For the MTJ memory cell are provided a write word line WWL for instructing a data write operation, a read word line RWL for instructing a data read operation, and a bit line BL serving as a data line for transmitting an electric signal corresponding to the level of storage data in the data read and write operations.
FIG. 42 is a conceptual diagram illustrating the data read operation from the MTJ memory cell.
Referring to FIG. 42, the magnetic tunnel junction MTJ has a magnetic layer FL having a fixed magnetic field of a fixed direction (hereinafter, also simply referred to as fixed magnetic layer FL), and a magnetic layer VL having a free magnetic field (hereinafter, also simply referred to as free magnetic layer VL). A tunnel barrier TB formed from an insulator film is provided between the fixed magnetic layer FL and free magnetic layer VL. According to the level of storage data, either a magnetic field of the same direction as that of the fixed magnetic layer FL or a magnetic field of the direction different from that of the fixed magnetic field FL has been written to the free magnetic layer VL in a non-volatile manner.
In reading the data, the access transistor ATR is turned ON in response to activation of the read word line RWL. As a result, a sense current Is flows through a current path formed by the bit line BL, magnetic tunnel junction MTJ, access transistor ATR and ground potential Vss. The sense current Is is supplied as a constant current from a not-shown control circuit.
The resistance value of the magnetic tunnel junction MTJ varies according to the relative relation of the magnetic field direction between the fixed magnetic layer FL and free magnetic layer VL. More specifically, in the case where the fixed magnetic layer FL and free magnetic layer VL have the same magnetic field direction, the magnetic tunnel junction MTJ has a smaller resistance value as compared to the case where both magnetic layers have different magnetic field directions.
Accordingly, in reading the data, a potential change at the magnetic tunnel junction MTJ due to the sense current Is varies according to the magnetic field direction stored in the free magnetic layer VL. Thus, for example, by starting supply of the sense current Is after precharging the bit line BL to a high potential, the level of storage data in the MTJ memory cell can be read by monitoring a potential level change on the bit line BL.
FIG. 43 is a conceptual diagram illustrating the data write operation to the MTJ memory cell.
Referring to FIG. 43, in writing the data, the read word line RWL is inactivated, and the access transistor ATR is turned OFF. In this state, a data write current for writing a magnetic field to the free magnetic layer VL is applied to the write word line WWL and bit line BL. The magnetic field direction of the free magnetic layer VL is determined by combination of the respective directions of the data write current flowing through the write word line WWL and bit line BL.
FIG. 44 is a conceptual diagram illustrating the relation between the respective directions of the data write current and magnetic field in the data write operation.
Referring to FIG. 44, a magnetic field Hx of the abscissa indicates the direction of a magnetic field H(WWL) produced by the data write current flowing through the write word line WWL. A magnetic field Hy of the ordinate indicates the direction of a magnetic field H(BL) produced by the data write current flowing through the bit line BL.
The magnetic field direction stored in the free magnetic layer VL is updated only when the sum of the magnetic fields H(WWL) and H(BL) reaches the region outside the asteroid characteristic line shown in the figure. In other words, the magnetic field direction stored in the free magnetic layer VL is not updated when a magnetic field corresponding to the region inside the asteroid characteristic line is applied.
Accordingly, in order to update the storage data of the magnetic tunnel junction MTJ by the data write operation, a current must be applied to both the write word line WWL and bit line BL. Once the magnetic field direction, i.e., the storage data, is stored in the magnetic tunnel junction MTJ, it is held therein in a non-volatile manner until a new data read operation is conducted.
The sense current Is flows through the bit line BL even in the data read operation. However, the sense current Is is generally set to a value that is smaller than the above-mentioned data write current by about one or two orders of magnitude. Therefore, it is less likely that the storage data in the MTJ memory cell is erroneously rewritten due to the sense current is during the data read operation.
The above-mentioned technical documents disclose a technology of forming an MRAM device, a random access memory, with such MTJ memory cells integrated on a semiconductor substrate.
FIG. 45 is a conceptual diagram showing the MTJ memory cells arranged in rows and columns in an integrated manner.
Referring to FIG. 45, with the MTJ memory cells arranged in rows and columns on the semiconductor substrate, a highly integrated MRAM device can be realized. FIG. 45 shows the case where the MTJ memory cells are arranged in n rows by m columns (where n, m is a natural number).
As described before, the bit line BL, write word line WWL and read word line RWL are provided for each MTJ memory cell. Accordingly, n write word lines WWLl to WWLn, n read word lines RWL to RWLn, and m bit lines BLl to BLm must be provided for the nxc3x97m MTJ memory cells.
Thus, for the MTJ memory cells, the independent word lines are generally provided for the read and write operations.
FIG. 46 is a diagram showing the structure of the MTJ memory cell formed on the semiconductor substrate.
Referring to FIG. 46, the access transistor ATR is formed in a p-type region PAR of a semiconductor main substrate SUB. The access transistor ATR has source/drain regions (n-type regions) 110, 120 and a gate 130. The source/drain region 10 is coupled to the ground potential Vss through a metal wiring formed in a first metal wiring layer M1. A metal wiring formed in a second metal wiring layer M2 is used as the write word line WWL. The bit line BL is formed in a third metal wiring layer M3.
The magnetic tunnel junction MTJ is formed between the second metal wiring layer M2 of the write word line WWL and the third metal wiring layer M3 of the bit line BL. The source/drain region 120 of the access transistor ATR is electrically coupled to the magnetic tunnel junction MTJ through a metal film 150 formed in a contact hole, the first and second metal wiring layers M1 and M2, and a barrier metal 140. The barrier metal 140 is a buffer material for providing electrical coupling between the magnetic tunnel junction MTJ and metal wirings.
As described before, in the MTJ memory cell, the read word line RWL is provided independently of the write word line WWL. In addition, in writing the data, a data write current for generating a magnetic field equal to or higher than a predetermined value must be applied to the write word line WLL and bit line BL. Accordingly, the bit line BL and write word line WWL are each formed from a metal wiring.
On the other hand, the read word line RWL is provided in order to control the gate potential of the access transistor ATR. Therefore, a current need not be actively applied to the read word line RWL. Accordingly, for the purpose of improving the integration degree, the read word line RWL is conventionally formed from a polysilicon layer, polycide structure, or the like in the same wiring layer as that of the gate 130 without forming an additional independent metal wiring layer.
Thus, integrating the MTJ memory cells on the semiconductor substrate requires a large number of wirings for the memory cells. Therefore, the total number of wirings is increased, resulting in increase in manufacturing cost. Moreover, since a large number of MTJ memory cells are always connected to the bit line BL, the bit line BL has a relatively large parasitic capacitance. Furthermore, the read word line RWL is formed from a polysilicon layer or polycide structure, as described above. As a result, it has been difficult to increase the read operation speed.
Even in writing the data, a relatively large data write current must be applied to the bit line BL. Moreover, the direction of the data write current must be controlled according to the level of write data, resulting in complicated circuitry for controlling the data write current.
It is an object of the present invention to achieve reduction in manufacturing cost by simplifying the structure of control circuitry for supplying a data write current in an MRAM device having MTJ memory cells.
It is another object of the present invention to improve the freedom of layout and thus reduce the layout area, i.e., the chip area, by separately providing respective drive circuits for read word lines and write word lines.
It is still another object of the present invention to achieve reduction in manufacturing cost by reducing the number of wirings required for each memory cell.
In summary, according to one aspect of the present invention, a thin film magnetic memory device includes a memory array, a plurality of write word lines, a plurality of bit line pairs, a data write control circuit, and a plurality of bit line current control circuits. The memory array has a plurality of magnetic memory cells arranged in rows and columns. Each magnetic memory cell has a resistance value that varies according to a level of storage data to be written when a data write magnetic field applied by first and second data write currents is larger than a predetermined magnetic field. The plurality of write word lines are provided corresponding to the respective rows of the magnetic memory cells, and are selectively activated according to an address selection result in a data write operation so as to cause the first data write current to flow therethrough. The plurality of bit line pairs are provided corresponding to the respective columns of the magnetic memory cells, and each includes first and second bit lines. In the data write operation, the data write control circuit sets one of the first and second bit lines included in one of the plurality of bit line pairs that is selected according to the address selection result, to one of a high potential state and a low potential state as well as sets the other bit line to the other potential state. The plurality of bit line current control circuits are provided respectively corresponding to the plurality of bit line pairs, for electrically coupling the corresponding first and second bit lines to each other in the data write operation so as to cause the second data write current to flow therethrough.
Accordingly, an advantage of the present invention mainly resides in the fact that the data write current can be made to flow through the short-circuited bit line pair as reciprocating current in the data write operation, and therefore the structure for controlling the data write current can be simplified.
According to another aspect of the present invention, a thin film magnetic memory device includes a memory array, a plurality of write word lines, a plurality of bit lines, a data line pair, a data write control circuit, a plurality of column selection gate circuits, and a plurality of bit line current control circuits. The memory array has a plurality of magnetic memory cells arranged in rows and columns. Each magnetic memory cell has a resistance value that varies according to a level of storage data to be written when a data write magnetic field applied by first and second data write currents is larger than a predetermined magnetic field. The plurality of write word lines are provided corresponding to the respective rows of the magnetic memory cells, for causing the first data write current to flow therethrough according to an address selection result in a data write operation. The plurality of bit lines are provided corresponding to the respective columns of the magnetic memory cells. The data line pair is provided in common to the plurality of bit lines, and is formed by first and second data lines. The data write control circuit sets one of the first and second data lines to one of a high potential state and a low potential state as well as sets the other data line to the other potential state in the data write operation. The plurality of column selection gate circuits are provided corresponding to the respective columns, for connecting the corresponding bit line to the first data line according to the address selection result. The plurality of bit line current control circuits are provided corresponding to the respective columns, for electrically coupling the corresponding bit line to the second data line so as to cause the second data write current to flow therethrough in the data write operation.
In such a thin film magnetic memory device, the direction of the data write current flowing through the open bit line can be set by controlling the respective potential levels on the first and second data lines forming the data line pair. Therefore, the structure for controlling the data write current can be simplified.
According to a still another aspect of the present invention, a thin film magnetic memory device includes a memory array, a plurality of read word lines, a plurality of write word lines, a plurality of write data lines, and a plurality of read data lines. The memory array has a plurality of magnetic memory cells arranged in rows and columns. Each magnetic memory cell includes a storage portion having a resistance value that varies according to a level of storage data to be written when a data write magnetic field applied by first and second data write currents is larger than a predetermined magnetic field, and a memory cell selection gate for passing a data read current therethrough into the storage portion in a data read operation. The plurality of read word lines are provided corresponding to the respective rows of the magnetic memory cells, for actuating the corresponding memory cell selection gate according to an address selection result in the data read operation. The plurality of write word lines are provided corresponding to the respective columns of the magnetic memory cells, and are selectively driven to an active state according to an address selection result in a data write operation so as to cause the first data write current to flow therethrough. The plurality of write data lines are provided corresponding to the respective rows, for causing the second data write current to flow therethrough in the data write operation. The plurality of read data lines are provided corresponding to the respective columns, for causing the data read current to flow therethrough in the data read operation.
In such a thin film magnetic memory device, the read word lines and the write word lines are provided respectively corresponding to the rows and columns of the magnetic memory cells. Accordingly, a circuit for selectively driving the read word lines and a circuit for selectively driving the write word lines can be independently provided. As a result, the freedom of layout can be improved, resulting in improvement in integration degree.
According to yet another aspect of the present invention, a thin film magnetic memory device includes a memory array, a plurality of read word lines, a plurality of write word lines, a plurality of common lines, and a current control circuit. The memory array has a plurality of magnetic memory cells arranged in rows and columns. Each magnetic memory cell includes a storage portion having a resistance value that varies according to a level of storage data to be written when a data write magnetic field applied by first and second data write currents is larger than a predetermined magnetic field, and a memory cell selection gate for passing a data read current therethrough into the storage portion in a data read operation. The plurality of read word lines are provided corresponding to the respective rows of the magnetic memory cells, for actuating the corresponding memory cell selection gate according to an address selection result in the data read operation. The plurality of write data lines are provided corresponding to one of the respective rows and the respective columns, for causing the first data write current to flow therethrough in the data write operation. The plurality of common lines are provided corresponding to the other of the respective rows and the respective columns. Each common line selectively receives supply of the data read current according to the address selection result in the data read operation. Each common line is selectively driven to a first potential so as to cause the second data write current to flow therethrough in the data write operation. The current control circuit couples and disconnects a second potential to and from each of the common lines in the data read and write operations, respectively, the second potential being different from the first potential.
In such a thin film magnetic memory device, the common line is capable of having both the function of the read data line in the data read operation and the function of the write word line in the data write operation. As a result, the number of wirings can be reduced, whereby reduction in manufacturing cost can be achieved.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.